`include "../codigo/Fetch.v"

module test_Fetch ( ) ;
    
    reg t_clock;
    reg t_reset;
    // Execute
    reg t_ex_if_stall;
    // Forwarding
    reg t_fw_if_id_stall;
    // Decode
    wire [31:0] t_if_id_proximopc;
    wire [31:0] t_if_id_instrucao;
    reg t_id_if_selfontepc;
    reg [31:0] t_id_if_rega;
    reg [31:0] t_id_if_pcimd2ext;
    reg [31:0] t_id_if_pcindex;
    reg [1:0] t_id_if_seltipopc;
    // Memory Controller
    wire t_if_mc_en;
    wire [31:0] t_if_mc_addr;
    reg [31:0] t_mc_if_data;
	
	Fetch t_fetch( .clock(t_clock),
		.reset(t_reset),
		.ex_if_stall(t_ex_if_stall),
		.fw_if_id_stall(t_fw_if_id_stall),
		.if_id_proximopc(t_if_id_proximopc),
		.if_id_instrucao(t_if_id_instrucao),
		.id_if_selfontepc(t_id_if_selfontepc),
		.id_if_rega(t_id_if_rega),
		.id_if_pcimd2ext(t_id_if_pcimd2ext),
		.id_if_pcindex(t_id_if_pcindex),
		.id_if_seltipopc(t_id_if_seltipopc),
		.if_mc_en(t_if_mc_en),
		.if_mc_addr(t_if_mc_addr),
		.mc_if_data(t_mc_if_data) );

	initial begin
			
		

		//Teste Reset
		$display("------------Inicio Testes Reset-------------");
		t_fetch.pc = #0 32'b1100;
		$display("Ciclo: %d\nReset: %d\nPC: %d\nif_id_proximopc: %d\nif_id_instrucao: %d\n", $time, t_reset, t_fetch.pc, t_if_id_proximopc, t_if_id_instrucao);

		t_reset = #2 1'b0;
		$display("Ciclo: %d\nReset: %d\nPC: %d\nif_id_proximopc: %d\nif_id_instrucao: %d\n", $time, t_reset, t_fetch.pc, t_if_id_proximopc, t_if_id_instrucao);

		t_reset = #2 1'b1;
		$display("Ciclo: %d\nReset: %d\nPC: %d\nif_id_proximopc: %d\nif_id_instrucao: %d\n", $time, t_reset, t_fetch.pc, t_if_id_proximopc, t_if_id_instrucao);

		$display("----------- Fim Testes Reset----------------");
	
		//Teste ex_if_stall

		$display("------------Inicio Testes Ex_if_stall-------------");
		t_fetch.if_id_instrucao = #2 32'b110011010;
		$display("Ciclo: %d\nfw_if_id_stall: %d\nPC: %d\nex_if_stall: %d\nClock: %d\nif_id_proximopc: %d\nif_id_instrucao: %d\n", $time, t_fw_if_id_stall, t_fetch.pc, t_ex_if_stall, t_clock, t_fetch.if_id_proximopc, t_fetch.if_id_instrucao);

		t_fetch.pc = #2 32'b1100;
		$display("Ciclo: %d\nfw_if_id_stall: %d\nPC: %d\nex_if_stall: %d\nClock: %d\nif_id_proximopc: %d\nif_id_instrucao: %d\n", $time, t_fw_if_id_stall, t_fetch.pc, t_ex_if_stall, t_clock, t_fetch.if_id_proximopc, t_fetch.if_id_instrucao);
	
		t_fw_if_id_stall = #0 1'b0;
		$display("Ciclo: %d\nfw_if_id_stall: %d\nPC: %d\nex_if_stall: %d\nClock: %d\nif_id_proximopc: %d\nif_id_instrucao: %d\n", $time, t_fw_if_id_stall, t_fetch.pc, t_ex_if_stall, t_clock, t_fetch.if_id_proximopc, t_fetch.if_id_instrucao);

		t_ex_if_stall = #2 1'b1;
		$display("Ciclo: %d\nfw_if_id_stall: %d\nPC: %d\nex_if_stall: %d\nClock: %d\nif_id_proximopc: %d\nif_id_instrucao: %d\n", $time, t_fw_if_id_stall, t_fetch.pc, t_ex_if_stall, t_clock, t_fetch.if_id_proximopc, t_fetch.if_id_instrucao);
		t_clock = #2 1'b1;
		$display("Ciclo: %d\nfw_if_id_stall: %d\nPC: %d\nex_if_stall: %d\nClock: %d\nif_id_proximopc: %d\nif_id_instrucao: %d\n", $time, t_fw_if_id_stall, t_fetch.pc, t_ex_if_stall, t_clock, t_fetch.if_id_proximopc, t_fetch.if_id_instrucao);
		t_clock = #2 1'b0;
		$display("Ciclo: %d\nfw_if_id_stall: %d\nPC: %d\nex_if_stall: %d\nClock: %d\nif_id_proximopc: %d\nif_id_instrucao: %d\n", $time, t_fw_if_id_stall, t_fetch.pc, t_ex_if_stall, t_clock, t_fetch.if_id_proximopc, t_fetch.if_id_instrucao);
		t_clock = #2 1'b1;
		$display("Ciclo: %d\nfw_if_id_stall: %d\nPC: %d\nex_if_stall: %d\nClock: %d\nif_id_proximopc: %d\nif_id_instrucao: %d\n", $time, t_fw_if_id_stall, t_fetch.pc, t_ex_if_stall, t_clock, t_fetch.if_id_proximopc, t_fetch.if_id_instrucao);
		t_ex_if_stall = #2 1'b0;
		$display("Ciclo: %d\nfw_if_id_stall: %d\nPC: %d\nex_if_stall: %d\nClock: %d\nif_id_proximopc: %d\nif_id_instrucao: %d\n", $time, t_fw_if_id_stall, t_fetch.pc, t_ex_if_stall, t_clock, t_fetch.if_id_proximopc, t_fetch.if_id_instrucao);

		$display("------------Fim Testes Ex_if_stall-------------");
		

		//Teste id_if_selfontepc
		$display("------------Inicio Testes id_if_selfontepc-------------");

		
		t_id_if_selfontepc = #2 1'b1;
		t_reset = #2 1'b0;
		t_reset = #2 1'b1;

		//sub-teste 1: entrada pelo id_if_pcimd2ext
		$display(">>>> Inicio sub-testes pcimd2ext <<<<");

		$display("\nCiclo: %d;\nClock: %d\nid_if_pcimd2ext: %d\nid_if_seltipopc: %d\nPC: %d\n------------------------------------------\n", $time, t_clock, t_id_if_pcimd2ext, t_id_if_seltipopc, t_fetch.pc); 	
		t_id_if_pcimd2ext = #2 32'b11100;
		t_id_if_seltipopc = #0 2'b00;
		$display("\nCiclo: %d;\nClock: %d\nid_if_pcimd2ext: %d\nid_if_seltipopc: %d\nPC: %d\n------------------------------------------\n", $time, t_clock, t_id_if_pcimd2ext, t_id_if_seltipopc, t_fetch.pc);
		t_clock = #2 1'b0;
		t_clock = #2 1'b1;
		$display("\nCiclo: %d;\nClock: %d\nid_if_pcimd2ext: %d\nid_if_seltipopc: %d\nPC: %d\n------------------------------------------\n", $time, t_clock, t_id_if_pcimd2ext, t_id_if_seltipopc, t_fetch.pc); 		

		t_reset = #2 1'b0;
		t_reset = #2 1'b1;

		//sub-teste 2: entrada pelo id_if_rega
		$display(">>>>> Inicio sub-testes rega <<<<<");
		$display("\nCiclo: %d;\nClock: %d\nid_if_rega: %d\nid_if_seltipopc: %d\nPC: %d\n------------------------------------------\n", $time, t_clock, t_id_if_rega, t_id_if_seltipopc, t_fetch.pc);
		t_id_if_rega = #2 32'b1000;
		t_id_if_seltipopc = #2 2'b01;
		$display("\nCiclo: %d;\nClock: %d\nid_if_rega: %d\nid_if_seltipopc: %d\nPC: %d\n------------------------------------------\n", $time, t_clock, t_id_if_rega, t_id_if_seltipopc, t_fetch.pc);
		t_clock = #2 1'b0;
		t_clock = #2 1'b1;
		$display("\nCiclo: %d;\nClock: %d\nid_if_rega: %d\nid_if_seltipopc: %d\nPC: %d\n------------------------------------------\n", $time, t_clock, t_id_if_rega, t_id_if_seltipopc, t_fetch.pc);
		
		t_reset = #2 1'b0;
		t_reset = #2 1'b1;

		//sub-teste 3: entrada pelo id_if_pcindex
		$display(">>>>> Inicio sub-testes pcindex <<<<<");
		$display("\nCiclo: %d;\nClock: %d\nid_if_pcindex: %d\nid_if_seltipopc: %d\nPC: %d\n------------------------------------------\n", $time, t_clock, t_id_if_pcindex, t_id_if_seltipopc, t_fetch.pc);
		t_id_if_pcindex = #2 32'b1110110100;
		t_id_if_seltipopc = #2 2'b10;

		$display("\nCiclo: %d;\nClock: %d\nid_if_pcindex: %d\nid_if_seltipopc: %d\nPC: %d\n------------------------------------------\n", $time, t_clock, t_id_if_pcindex, t_id_if_seltipopc, t_fetch.pc);
		t_clock = #2 1'b0;
		t_clock = #2 1'b1;


		$display("\nCiclo: %d;\nClock: %d\nid_if_pcindex: %d\nid_if_seltipopc: %d\nPC: %d\n------------------------------------------\n", $time, t_clock, t_id_if_pcindex, t_id_if_seltipopc, t_fetch.pc);

		t_reset = #2 1'b0;
		t_reset = #2 1'b1;
		
		//sub-teste 4: valor pré-definido
		$display(">>>>>> Inicio sub-teste valor pré-definido <<<<<<");
		$display("\nCiclo: %d;\nClock: %d\nid_if_seltipopc: %d\nPC: %d\n------------------------------------------\n", $time, t_clock, t_id_if_seltipopc, t_fetch.pc);
		t_id_if_seltipopc = #2 2'b11;
		$display("\nCiclo: %d;\nClock: %d\nid_if_seltipopc: %d\nPC: %d\n------------------------------------------\n", $time, t_clock, t_id_if_seltipopc, t_fetch.pc);
		t_clock = #2 1'b0;
		t_clock = #2 1'b1;

		$display("\nCiclo: %d;\nClock: %d\nid_if_seltipopc: %d\nPC: %d\n------------------------------------------\n", $time, t_clock, t_id_if_seltipopc, t_fetch.pc);
		$display("Fim selfontepc = 1");
		t_id_if_selfontepc = #2 1'b0;
		t_reset = #2 1'b0;
		t_reset = #2 1'b1;
		//Teste com selfontepc 0
		$display("\nCiclo: %d;\nClock: %d\nPC: %d\n------------------------------------------\n", $time, t_clock, t_fetch.pc);
		t_clock = #2 1'b0;
		t_clock = #2 1'b1;
		$display("\nCiclo: %d;\nClock: %d\nPC: %d\n------------------------------------------\n", $time, t_clock, t_fetch.pc);
		

		t_reset = #2 1'b0;
		t_reset = #2 1'b1;

		//Teste com mc_if_data
		$display("\nCiclo: %d\n->Sinais de Controle:\nex_if_stall: %d\nfw_if_id_stall: %d\nreg_if_mc_en: %d\n\n->Registradores:\nmc_if_data: %d\nif_id_instrucao: %d\n", $time, t_ex_if_stall, t_fw_if_id_stall, t_fetch.reg_if_mc_en, t_mc_if_data, t_fetch.if_id_instrucao);

		t_ex_if_stall = #2 1'b0;
		t_fw_if_id_stall = #2 1'b0;

		$display("\nCiclo: %d\n->Sinais de Controle:\nex_if_stall: %d\nfw_if_id_stall: %d\nreg_if_mc_en: %d\n\n->Registradores:\nmc_if_data: %d\nif_id_instrucao: %d\n", $time, t_ex_if_stall, t_fw_if_id_stall, t_fetch.reg_if_mc_en, t_mc_if_data, t_fetch.if_id_instrucao);

		t_mc_if_data = #2 32'b110100100100;

		$display("\nCiclo: %d\n->Sinais de Controle:\nex_if_stall: %d\nfw_if_id_stall: %d\nreg_if_mc_en: %d\n\n->Registradores:\nmc_if_data: %d\nif_id_instrucao: %d\n", $time, t_ex_if_stall, t_fw_if_id_stall, t_fetch.reg_if_mc_en, t_mc_if_data, t_fetch.if_id_instrucao);

		t_clock = #2 1'b0;
		t_clock = #2 1'b1;
		
		$display("\nCiclo: %d\n->Sinais de Controle:\nex_if_stall: %d\nfw_if_id_stall: %d\nreg_if_mc_en: %d\n\n->Registradores:\nmc_if_data: %d\nif_id_instrucao: %d\n", $time, t_ex_if_stall, t_fw_if_id_stall, t_fetch.reg_if_mc_en, t_mc_if_data, t_fetch.if_id_instrucao);
	end
endmodule
